1. Field of the Invention
The present invention relates to a memory controller which might be implemented in various ways such as, for example, in communication system architecture. The memory controller can be selectively configured to allow concurrent DMA and CPU accesses to memory or non-concurrent CPU access only.
2. Description of the Related Art
A recent trend in the modern work place is for individuals to work at remote sites and periodically connect to an office or central data site. Those individuals are often termed "telecommuters", and are defined as workers or employees who work from a remote site within their home, that site being connected to the central, corporate office. Another recent trend in the workplace is that of remote small offices or branch offices, wherein a group of workers or employees are situated in a location remote from the corporate headquarters. Those individuals are also electronically connected to the corporate office/headquarters. This movement away from the corporate or central site, and the benefit gained by avoiding a physical commute appears to be a trend which is here to stay. In all likelihood, this trend will continue given the transient nature by which most modern workers operate.
Remotely situated workers require transparent connectivity not only to the corporate office but also to the office's local area network (LAN). As corporations move away from mainframe based systems to personal computer (PC) based systems linked together by LANs, the options for remote connectivity have improved. In general, PCs and LANs facilitate remote access to the computing resources of the corporate office or corporate headquarters. Remote connectivity is also made possible with the arrival of affordable, reliable, digital telecommunications services and inexpensive network hardware. Currently, a variety of digital telecommunications services now support remote connections to enterprise networks, among these being Frame Relay Integrated Service Digital Network (ISDN), asynchronous transfer mode (ATM), digital data service and T1, among others.
Recent advances allow modern communication systems to handle increasingly large amounts of data. Those communications systems are many times required to accommodate integrated services, such as voice, data and video, on a single communication medium. Data provided through a communications system can either be isochronous or real-time. The communication system is correspondingly required to maintain a desired level of throughput or data transfer in order to guarantee real-time delivery of, for example, audio and/or video.
As with computer systems, communication systems generally comprise various logic components connected by one or more system busses. Those busses provide a transfer path for control and data information between each of the various logic components. In many systems, the system bus becomes a bottleneck for the transfer of data between the various logic components. Therefore, an improved system and method is desired which provides more efficient bus utilization for increased data throughput. That throughput is highly desirable in communication systems which must transfer large amounts of data in, for example, real time.
An important aspect of throughput is control of data to and from a memory media. For example, it may be desirable to utilize a communications system having a dynamic random access memory (DRAM). It would be further desirous to transfer data to and from the memory from various bus masters, i.e., bus masters being those which obtain mastership of the system bus. For example, a modern communications system may call upon data transfer from a remote site as well as data transfer from the local PC's CPU. That data transfer occurs to and from the DRAM with rapidity. It would therefore be desirable to employ a memory controller within the communications system which can provide more efficient data transfer between the local DRAM and both the local CPU as well as a local bus master controller linked, for example, to a computer located remote from the local CPU.
Accordingly, an improvement must be made by which concurrent or non-concurrent data transfers can take place between the local DRAM and the local CPU and/or a remote computer. Those data transfers must be performed in such a way that a bottleneck on the system bus and/or DRAM interface bus is substantially avoided.